Extreme broadband integrated photonic electronic receiver on silicon substrate

The bandwidth of electronic circuits is fundamentally limited by the transit frequency of avail-able transistors. As a consequence, the exceptionally high transmission capacity of optical communication systems can only be exploited with massive parallel usage of electronic cir-cuits. The basic idea of the project’s first phase was a photonic preprocessing circuit followed by a special time interleaving electronic demultiplexing circuit. The aim of the second phase of the SPP2111 is the expansion of the concept to a fully reconfigurable ultra-broadband dual polarization photonic receiver in combination with a massive parallelization of electronic cir-cuits and demultiplexed analog outputs. In contrast to the hybrid setup of the first phase, now a single chip monolithic integration is projected. The bandwidth of the total system will be im-proved by different steps: The optical input bandwidth will be increased by redesigning the state-of-the-art grating couplers to cover more than 50 x 200 GHz WDM channels. Data throughput is maximised by redesigning of the amplifier- and demux-stages and applying po-larisation multiplex. The intended reconfigurability of the receiver is enabled by optical non blocking switch fabrics that are based on low-loss multi-mode interferometers and gener-alized Mach-Zehnder interferometers. In this second phase, all structures, including polariza-tion multiplex, switch fabric, photodiode, amplifiers and the analog demultiplexer parts will be monolithically integrated on a single chip in the EPIC technology of IHP. Due to the demulti-plexing, the electrical bandwidth requirements at the outputs are more relaxed, thus subse-quent ADCs can be connected via bond wires.